1. Field of the Invention
The present invention relates to a reset circuit which is used in, for example, bit lines or data bus lines of memory devices of an integrated circuit device.
2. Description of the Prior Art
Reset circuits for resetting the state of a first and second circuit systems to an original state, and the operations of said reset circuits, are illustrated in FIGS. 1, 2, 3A and 3B. In FIG. 1, the first circuit system and the second circuit system are represented by the data bus line 1 and the data bus line 2, respectively, which are connected through the flip-flop 4 consisting of the FETs (field effect transistors) Q.sub.5, Q.sub.6, Q.sub.7 and which Q.sub.8 and has its two input and output terminals connected to the data bus lines 1 and 2, respectively. The reset circuit 3 comprises the FETs Q.sub.1, Q.sub.2 and Q.sub.3, the gates of which are connected to a common terminal to which the clock signal .phi..sub.1 is supplied. The FET Q.sub.9 is connected to the FETs Q.sub.7 and Q.sub.8 which are included in the flip-flop 4. The clock signal .phi..sub.2 which causes the flip-flop 4 to switch on and off is supplied to the gate of the FET Q.sub.9.
The reset operation in the system shown in FIG. 1 is explained with reference to the waveforms illustrated in FIG. 2. It is presumed that the operation to read-out information from the memory through the data bus lines 1 and 2 is completed. At this moment, the voltage of the power source EL is V.sub.DD, the voltage V(1) of the first circuit 1 is "0" and the voltage V(2) of the second circuit 2 is "V.sub.DD -V.sub.TH ", where V.sub.DD is the drain supply direct current voltage of the FETs Q.sub.1 and Q.sub.2, V.sub.Th6 is the threshold voltage of the FET Q.sub.6. The reset operation is achieved if this condition is changed into the condition in which the potentials of the first circuit 1 and the second circuit 2 have the same value. In order to achieve the reset operation, at first, the clock signal .phi..sub.1 having the value of V.sub.DD is supplied to the gates of the FETs Q.sub.1, Q.sub.2 and Q.sub.3. Thus, the FET Q.sub.1 in an OFF state is caused to become in an ON state, and the first circuit 1 is charged from the power source EL, and accordingly the potential V(1) of the first circuit 1 rises to potential P. At the same time, the FET Q.sub.3, which is in an OFF state is caused to become in an ON state, and the charge is caused to move from the second circuit 2 to the first circuit 1, and accordingly the potential V(2) of the second circuit 2 falls to potential P. Thus, the FET Q.sub.2 which is in an OFF state is caused to become in an ON state because of the lowering of the potential of the second circuit 2, and the charging commences of the both circuits 1 and 2 from the power source EL from the reset circuit 3. Accordingly, the potentials of the first circuit 1 and the second circuit 2 which were at the level P start together to rise up to the potential "V.sub.DD -V.sub.TH6 " so that the reset operation is completed assuming that V.sub.TH1 =V.sub.TH2 =V.sub.TH.
The problem of the system shown in FIG. 1 under the condition when the threshold voltages of the FETs Q.sub.1, Q.sub.2 and Q.sub.3 are the same value V.sub.TH is as follows. That is, after the instant t.sub.3 at which the first and the second circuits are reset to the potential "V.sub.DD -V.sub.TH ", if the potential of the first circuit 1 rises up to the value "V.sub.DD -V.sub.TH +.alpha." as illustrated in the portion A of FIG. 2 because of some noise effect, due, for example to an electrostatic coupling with a neighbouring electirc circuits, while the potential of the second circuit 2 remains the value "V.sub.DD -V.sub.TH ", it is possible that an erroneous judgement is incurred in the next reading-out of the memory. The cause of such an erroneous judgement is explained as follows. In order to read-out the memory cell storing information "0", the judgement of the potential of the first circuit 1 with reference to the potential of the second circuit 2 by means of flip-flop 4 is effected by lowering the potential of the first circuit to which said memory cell is connected and supplying the clock signal .phi..sub.2 to the gate of the FET Q.sub.9. If the potential of the first circuit was "V.sub.DD -V.sub.TH +.alpha." and the potential of the first circuit is then caused to fall to the value approximately "V.sub.DD -V.sub.TH " by the above-mentioned potential lowering, such potential of approximately "V.sub.DD -V.sub.TH " of the first circuit is not substantially lower than the potential "V.sub.DD -V.sub.TH " of the second circuit 2. Therefore, the erroneous judgement that the information stored in the above-mentioned memory cell is not "0" but "1" is incurred. The above-described reset circuit is disclosed in, for example, U.S. Pat. No. 3,678,473.
In other words, when the potential of the first circuit 1 is higher by .beta. than that of the second circuit 2 and if a low voltage which is smaller than .beta. is applied to the first circuit 1 to reduce the potential of the first circuit 1 and is amplified by the flip-flop 4 consisting of the FETs Q.sub.5 through Q.sub.8, the flip-flop 4 causes the potential of the first circuit 1 to become "1", i.e., "HIGH", and the potential of the second circuit 2 to become "0", i.e., "LOW". Contrary to this, when no unequality of the potential exists between the first circuit 1 and the second circuit 2 and if a low voltage is applied to the first circuit 1 to reduce the potential of the first circuit 1 and is amplified by the flip-flop 4, the flip-flop 4 causes the potential of the first circuit to become "0", i.e., "LOW", and the potential of the second circuit 2 to become "1", i.e., "HIGH", so that a correct amplification takes place.
Since, in general, very low voltage signals are supplied from a memory cell to a bit line and from a bit line to a data bus line in a memory circuit, the erroneous operation described above can occur when an unequality of the potential exists between the first circuit 1 and the second circuit 2.
In order to avoid the above-mentioned erroneous judgement, the systems as shown in FIGS. 3A and 3B have been proposed. In the system shown in FIG. 3A, the gate signal .phi..sub.3 for the FET Q.sub.3 is selected higher than the gate signal .phi..sub.1 ' for the FETs Q.sub.1 and Q.sub.2. In the system shown in FIG. 3B, a FET Q.sub.4 is connected between the first circuit 1 and the second circuit 2 in parallel with the FET Q.sub.3. A gate signal .phi..sub.3 ' which is higher than the gate signal .phi..sub.1 is supplied to the gate of the FET Q.sub.4. Thus, in the systems shown in FIGS. 3A and 3B, it is possible to avoid the erroneous judgement which occurs in FIG. 1.
However, the systems shown in FIGS. 3A and 3B are not the best solutions of the problem, because in the systems shown in FIGS. 3A and 3B it is necessary to provide the gate signals .phi..sub.3 and .phi..sub.3 ', to make the gate signals .phi..sub.3 and .phi..sub.3 ' higher than the gate signals .phi..sub.1 and .phi..sub.1 ', to provide electric conductors to supply the gate signals .phi..sub.3, .phi..sub.3 ' to the gates of the FETs Q.sub.3 and Q.sub.4, and to acquire a predetermined space for locating the FET Q.sub.4.
The present invention is proposed for the purpose of providing a solution to the above explained problems.